During the semiconductor manufacturing process, particularly in large scale manufacturing process, the short of the semiconductor device incurs frequently due to the overlay deviation between the metal and the contact holes. Consequently, it causes the instability of the semiconductor device yield. The overlay safety zone assessments are required in order to monitor the process stability.
In the prior art, there is no good method for assessing the overlay safety zone during the production of semiconductor. The remedy measures are taken until the problem occurs, which would resulted in the passive effect of controlling the stability of the process. Hence, the quality of the product is affected in the production process.
Chinese patent (CN 100576526C) discloses a circuit structure to realize interconnection of the upper and lower metal, which comprises the upper metal and the lower metal mounted in the contact hole between the upper metal and the lower metal. The said upper metal and lower metal are aligned strictly with each other. The contact hole denominated in line forms an offset of different aperture from 0 to 0.5 with the lower metal and offset value and offset direction between two adjacent lines of contact holes are different. When the contact holes of the left most line offset to left with the value from 0 to 0.5, the left side of the adjacent line offset to right with the value from 0 to 0.5. The invention can timely detect and identify the offset between the contact hole and the lower metal as well as the titanium lacking in the process, which is applicable to process development of the semiconductor integrated circuit. The patent can detect and confirm the offset and titanium deletion process issues in the through hole and the lower metal, but it did not solve the problem of determining the safety zone of the overlay before the production of the semiconductor is ensured.
Chinese patent (CN 101266937A) discloses a method for testing the overlay offset of semiconductor process. It comprises forming an overlay offset measurement target, which includes a first feature on a first layer and a second feature on a second layer. The first feature and the second feature have the first preconfigured overlay offset. The target is irradiated. The reflectivity of the irradiated target is determined. An overlay offset for the first layer and the second layer is calculated using the determined reflectivity. The patent calculates the preconfigured overlay offset of the first layer and the second layer by using the reflectivity. It only disclosed a method of measuring an overlay offset without solving the problem of determining the safety zone of the overlay before the production of the semiconductor is ensured.
Hence, the safety zone of the overlay is not determined before the production of the semiconductor is ensured currently.